1. Field of the Invention
The present invention relates to a semiconductor device suitable for high integration and a method of manufacturing the same, particularly to a semiconductor device suitably applicable to a semiconductor memory, such as a DRAM or a flash memory, having an element region and a peripheral circuit region.
2. Description of the Related Art
In recent years, there is a strong tendency to demand not only high integration but also a higher added value of a semiconductor device. For example, for a DRAM hybrid chip having a memory cell and a logic circuit (a peripheral circuit of the memory cell), which has received a great deal of attention as a semiconductor memory in a new field, a technique of forming a metal silicide that reduces the resistance value in the source and the drain of a transistor constructing the logic circuit is indispensable. In application of this technique, however, a fundamental problem is posed in which no metal silicide can be used for the source and the drain of the transistor constructing the memory cell of a DRAM from the viewpoint of refresh characteristics. Hence, for the source and the drain of the transistor, the memory cell side and the logic circuit side must be independently formed.
However, the above-described technique has an aspect inconsistent with the requirement of a highly integrated memory cell. More specifically, as the degree of integration rises, the alignment margin of contact holes becomes strict. To relax it, a nitride film with an etching rate lower than that of an oxide film is formed as a passivation film covering the transistor, and a borderless contact technique (BLC) or a self-alignment contact technique (SAC) of forming a contact hole in self-alignment is used. In this example, use of the self-aligning technique described above poses a problem to be described below in detail.
When the memory cell size is reduced by high integration, the distance between adjacent gate electrodes of the memory cell also shortens. In this case, as shown in FIG. 31A, when the distance between gate electrodes 301 shortens, an element interval 302 between the gate electrodes 301 becomes zero due to a BLC or SAC nitride film 306. This disables BLC or SAC as a preprocess for formation of a metal silicide, nothing to say of metal silicide formation.
As a countermeasure against this problem, a technique has been proposed in which after formation of the gate electrodes 301, a thin nitride film 303 for SAC, which has a thickness of about 30 nm, and an oxide film having a predetermined thickness are sequentially formed, and then a side wall 304 is formed on the entire surface of the structure by anisotropic etching, as shown in FIG. 31B. In this case, however, since a metal silicide need be formed on only the transistor on the logic circuit side, the source/drain surface of the transistor on the logic circuit side must be exposed by etching while masking the structure on the memory cell side. After formation of a metal silicide, a BLC nitride film 305 is formed. At this time, since the interval between the gate electrodes 301 is small, the gap between the side walls 304 is filled with the nitride film 305, as shown in FIG. 31B, so the nitride film 305 is substantially very thick when viewed from the upper side in forming a contact hole. This disables SAC on the memory cell side.
As described above, the requirement for reduction of resistance in the transistor of the logic circuit and that for an increase in the degree of integration of the entire memory cell portion and the logic circuit portion have tradeoff relationships. It is very difficult to meet these requirements simultaneously.